1. Field of the Invention
The present invention relates to a PLL circuit and a method of controlling the same.
2. Description of Related Art
In recent years, speed-up of a high definition multimedia interface (HDMI) is remarkable. One of the most important components of transmission/reception circuits conforming to the HDMI is a wideband phase locked loop (PLL). A PLL provided in the reception circuit receives a reference clock, which is transmitted from the transmission circuit, through an HDMI clock channel. The PLL outputs a clock obtained by multiplying the frequency of the reference clock. In this case, the clock output from the PLL is required to have a frequency corresponding to a transmission rate of an HDMI data channel. The frequency of the HDMI data channel varies in a range from several hundred MHz to several GHz. In other others, the PLL provided in the reception circuit is required to accurately lock (synchronize) the data cannel having such a wide frequency range. Moreover, random jitter of the clock output from the PLL is required to be suppressed below a predetermined value which is set depending on a transmission error rate or the like.
Reference is now made to FIG. 4 showing a PLL circuit of a related art. The PLL circuit shown in FIG. 4 includes a phase frequency detector (hereinafter abbreviated as “PFD”) 301, a charge pump (hereinafter abbreviated as “CP”) 302, a loop filter (hereinafter abbreviated as “LPF”) 303, a voltage controlled oscillator (hereinafter abbreviated as “VCO”) 305, a 1/N programmable frequency divider 307, and a 1/M programmable frequency divider 309.
The PFD 301 receives a reference clock 310 which is externally supplied and a comparison clock which is obtained by dividing the frequency of an output clock of the PLL circuit into 1/M (M is an integer equal to or greater than 1; frequency division ratio M). The PFD 301 detects a phase difference between the two signals and outputs a pulse signal corresponding to the phase difference. The CP 302 outputs a voltage signal corresponding to the pulse signal output from the PFD 301. The LPF 303 converts the signal output from the CP 302 into a DC signal, and outputs the converted signal as a control voltage 304. The VCO 305 outputs a clock signal having a frequency corresponding to the control voltage 304 as a VCO output clock 306. The 1/N programmable frequency divider 307 divides the frequency of the VCO output clock 306 into 1/N (N is an integer equal to or greater than 1; frequency division ratio N), and outputs the clock thus obtained as an output clock 308 of the PLL circuit. The 1/M programmable frequency divider 309 divides the frequency of the output clock 308 into 1/M (M is an integer equal to or greater than 1; frequency division ratio M), and outputs the clock thus obtained as the comparison clock of the PFD 301. Now, consideration is given to a case where the frequency division ratio of the 1/N programmable frequency divider 307 is “1” (N=1). In this case, the PLL circuit outputs the output clock 308 which is obtained by multiplying the frequency of the reference clock 310 by M.
FIG. 5 shows a typical relation between the control voltage 304 input to the VCO 305 and the frequency of the VCO output clock 306. As shown in FIG. 5, when the control voltage 304 input to the VCO 305 increases, the frequency of the VCO output clock 306 increases in proportion to the voltage.
FIG. 6 shows a typical relation between the frequency of the VCO output clock 306 and random jitter of the VCO output clock 306. As shown in FIG. 6, in general, when the frequency of the VCO output clock 306 exceeds a certain frequency range, the random jitter of the VCO output clock 306 increases rapidly. Similarly, when the frequency of the VCO output clock 306 falls below a certain frequency range, the random jitter of the VCO output clock 306 increases rapidly. The example of FIG. 6 shows a state where the random jitter increases rapidly when the frequency of the VCO output clock 306 is lower than F1 and when the frequency of the VCO output clock 306 is higher than F2. For example, an upper limit of the random jitter allowed by the PLL circuit is represented by R1. In this case, in the example shown in FIG. 6, the value of the random jitter is equal to or smaller than R1 when the frequency of the VCO output clock 306 is in a range from F1 to F2.
On the other hand, a minimum frequency required for the output clock 308 of the PLL circuit is represented by FL. A maximum frequency of the output clock 308 required for the PLL circuit is represented by FH (where FL<FH). In this case, it is desirable that all the frequencies of the output clock 308 of the PLL circuit fall within a frequency range from FL to FH, while the frequency division ratio of the 1/N programmable frequency divider 307 is maintained at N=1. However, in practice, it is extremely difficult to satisfy the requirement for low random jitter in such a wide frequency range.
Referring to FIGS. 5 and 6, consideration is given to a case where the frequency division ratio of the 1/N programmable frequency divider 307 is “1” (N=1), for example. That is, consideration is given to a case where the frequency of the output clock 308 is equal to the frequency of the VCO output clock 306. In this case, as shown in FIG. 6, when the frequency of the VCO output clock 306 is equal to FH, the random jitter is equal to or smaller than the allowable value R1. Meanwhile, when the frequency of the VCO output clock is equal to FL, the random jitter exceeds the allowable value R1. As shown in FIG. 5, in order to set the minimum frequency FL of the VCO output clock 306 to be equal to or higher than F1, the control voltage 304 needs to be increased. For this reason, the PLL circuit preferably includes a function of controlling the frequency division ratio of the 1/N programmable frequency divider 307 and the like. This makes it possible to automatically adjust the control voltage 304 to indicate a value in a range from V1 to V2 at all times. An example of such a control method is disclosed in Japanese Unexamined Patent Application Publication No. 2005-143030.
FIG. 8 shows a PLL clock signal generation circuit disclosed in Japanese Unexamined Patent Application Publication No. 2005-143030. The circuit shown in FIG. 8 includes a phase frequency detector (PFD) 101, a charge pump (CP) 102, a filter (LPF) 103, a voltage controlled oscillator (VCO) 104, a first frequency divider 105, a second frequency divider 106, and a multiplication ratio control circuit 107. As shown in FIG. 9, the multiplication ratio control circuit 107 includes a first Schmitt trigger circuit 201 for detecting an upper limit of a reference voltage, a second Schmitt trigger circuit 202 for detecting a lower limit of the reference voltage, an AND gate 203 for detecting a state, an NOR gate 204 for detecting a state, a D flip-flop 205 for switching the frequency dividers, an AND gate 206, and an OR gate 207.
A reference voltage (control voltage) LPFIN output from the filter 103 is input to the voltage controlled oscillator 104, and is also input to the two Schmitt trigger circuits 201 and 202 included in the multiplication ratio control circuit 107. As shown in FIG. 10, in the Schmitt trigger circuit 201, when the reference voltage LPFIN exceeds an upper limit VCH of a voltage range in which the voltage controlled oscillator 104 normally operates, the output signal changes from the “L” state to the “H” state. Meanwhile, as shown in FIG. 11, in the Schmitt trigger circuit 202, when the reference voltage LPFIN falls below a lower limit VCL of the voltage range in which the voltage controlled oscillator 104 normally operates, the output signal changes from the “H” state to the “L” state.
The PLL clock signal generation circuit shown in FIG. 8 is intended to maintain a correct locked (synchronized) state even if the frequency range of the reference clock is increased when the input voltage range in which the voltage controlled oscillator 104 normally operates is narrow.
To achieve this function, the multiplication ratio control circuit 107 controls the frequency division ratio of each of the first frequency divider 105 and the second frequency divider 106 so that the value of the reference voltage LPFIN is constantly maintained within the voltage range in which the voltage controlled oscillator 104 normally operates (i.e., a voltage range from the lower limit VCL to the upper limit VCH; hereinafter simply referred to as “lower limit VCL” and “upper limit VCH”). Specifically, when the Schmitt trigger circuit 201 detects that the reference voltage LPFIN exceeds the upper limit VCH, the frequency division ratio of each of the first frequency divider 105 and the second frequency divider 106 is decreased by one step. That is, the frequency of a comparison clock DIVOUT which is input to the phase frequency detector 101 is increased by one step. In this case, due to a correction made by the phase frequency detector 101, the oscillation frequency of the voltage controlled oscillator 104 decreases. That is, the reference voltage LPFIN decreases. Meanwhile, when the Schmitt trigger circuit 202 detects that the reference voltage LPFIN falls below the lower limit VCL, the frequency division ratio of each of the first frequency divider 105 and the second frequency divider 106 is increased by one step. That is, the frequency of the comparison clock DIVOUT input to the phase frequency detector 101 is decreased by one step. In this case, due to a correction made by the phase frequency detector 101, the oscillation frequency of the voltage controlled oscillator 104 increases. As a result, the reference voltage LPFIN increases.
Even when the PLL circuit is normally locked and operated, the reference voltage LPFIN input to the voltage controlled oscillator 104 constantly fluctuates by a small amount due to a ripple voltage component output from the filter 103. Accordingly, when the reference voltage LPFIN indicates a value near the upper limit VCH or the lower limit VCL, the operation of the PLL circuit may become unstable. To avoid such a phenomenon, in the circuit shown in FIG. 8, the Schmitt trigger circuits 201 and 202 having hysteresis characteristics control the reference voltage LPFIN. Thus, even when the reference voltage LPFIN fluctuates due to the influence of the ripple voltage, the multiplication ratio control circuit 107 can output a stable control signal LPFOUT. Therefore, the operation of the PLL circuit can be stabilized.
As described above, in the PLL clock generation circuit shown in FIG. 8, the reference voltage LPFIN input to the voltage controlled oscillator 104 is controlled at a value within the voltage range in which the voltage controlled oscillator 104 normally operates (i.e., the voltage range from the lower limit VCL to the upper limit VCH). Herein, proper values (ideal values) of the upper limit VCH and the lower limit VCL are referred to as “VCH_ideal” and “VCL_ideal”, respectively. There are various possible methods of determining the ideal values VCH_ideal and VCL_ideal. For example, a method of determining the ideal values by performing a circuit simulation on the voltage controlled oscillator 104, or a method of determining the ideal values based on a measurement result of a device mounted in the voltage controlled oscillator 104 may be employed.
In this case, it is extremely important to match the upper limit VCH and the lower limit VCL with the ideal values VCH_ideal and VCL_ideal, respectively, as accurately as possible. If the upper limit VCH is set to a value greater than the ideal value VCH_ideal, the reference voltage LPFIN deviates from the normal operating range of the voltage controlled oscillator 104, as a result of automatic adjustment. Similarly, when the lower limit VCL is set to a value smaller than the ideal value VCL_ideal, the reference voltage LPFIN deviates from the normal operating range of the voltage controlled oscillator 104, as a result of automatic adjustment. This leads to a fear that the PLL fails to operate properly. Meanwhile, when the upper limit VCH is set to a value smaller than the ideal value VCH_ideal, the reference voltage LPFIN does not take any value within the entire normal operating range of the voltage controlled oscillator 104. Similarly, when the lower limit VCL is set to a value greater than the ideal value VCL_ideal, the reference voltage LPFIN does not take any value within the entire normal operating range of the voltage controlled oscillator 104. In other words, excessively strict limitations are imposed on the operating range of the PLL circuit.
In the related art shown in FIG. 8, it appears that values generated during the actual circuit operation are set as the ideal values VCH_ideal and VCL_ideal. That is, in this example, it appears that threshold voltages determined by the actual operation of each of the Schmitt trigger circuits 201 and 202 are set as the ideal values VCH_ideal and VCL_ideal. In general, however, threshold values of the Schmitt trigger circuits are susceptible to variations in a manufacturing process, operating voltage, operating temperature, and the like of an LSI. Accordingly, the threshold voltage of each Schmitt trigger circuit may fluctuate by several tens of percent of a power supply voltage due to the influence of such variations. Therefore, it is difficult for the circuit shown in FIG. 8 to accurately detect that the reference voltage LPFIN indicates a value within the normal operating range (i.e., a value within a range from VCH_ideal to VCL_ideal). In other words, it is difficult for the circuit shown in FIG. 8 to automatically adjust the clock frequency accurately. Suppose that a function of adjusting the upper limit VCH and the lower limit VCL in response to a control signal externally supplied is provided so as to cope with a case where there is a difference in characteristics of the voltage controlled oscillator 104 between an electrical simulation result and a measurement result of an actual LSI, for example. Even in such a case, it is difficult to adjust the values of the upper limit VCH and the lower limit VCL themselves, since the threshold value of each Schmitt trigger circuit cannot be determined with accuracy.
FIG. 12 shows a PLL circuit disclosed in Published Japanese Translation of PCT International Publication for Patent Application, No. 2001-520471. The circuit shown in FIG. 12 includes a PFD 14, a loop filter (LPF) 18, a VCO 20, a CLK frequency divider 22, a determination circuit 30, and a control unit 32. According to the technique disclosed in Published Japanese translation of PCT International Publication for Patent Application, No. 2001-520471, when the frequency of a reference clock input to the PLL circuit has a wide frequency range, the frequency multiplication ratio of the PLL circuit is automatically adjusted. Thus, it is intended that the output clock frequency of the PLL circuit is maintained relatively constant. As shown in FIG. 12, the determination circuit 30 determines whether a voltage (control voltage) input to the VCO 20 falls within a set voltage range. Then, the control unit 32 controls the multiplication ratio of the CLK frequency divider 22 based on the determination result. Thus, the frequency of the clock signal output from the PLL circuit is stabilized. In the circuit shown in FIG. 12, however, there is disclosed no method to control a control voltage of a circuit having hysteresis characteristics. Accordingly, there is a fear that the operation of the PLL circuit becomes unstable due to a small voltage fluctuation.
The PLL circuit and control method therefor disclosed in Japanese Unexamined Patent Application Publication No. 2002-208857 are intended to automatically adjust the oscillation frequency range of the PLL circuit. The PLL circuit disclosed in Japanese Unexamined Patent Application Publication No. 2002-208857 includes a voltage-controlled variable oscillator (FIG. 13) capable of controlling the oscillation frequency range stepwise. As shown in FIG. 13, the magnitudes of capacitances added to oscillation nodes of an LC tank-type voltage controlled oscillator are switched by control signals CONT0, CONT1, CONT2, and CONT3, thereby controlling the oscillation frequency of the voltage controlled oscillator. However, also in the circuit shown in FIG. 13, there is disclosed no method to control a control voltage of a circuit having hysteresis characteristics. Accordingly, there is a fear that the operation of the PLL circuit becomes unstable due to a small voltage fluctuation.